The present invention relates to a transmission system comprising an echo canceler for removing an echo component echoing from a sending side to a receiving side, and a timing regenerating unit for regenerating sampling timing at the A/D conversion from a received A/D converted signal, and more specifically to a jitter compensating device for compensating a phase jump (jitter) generated in the timing regenerating unit at echo cancellation.
A two-wire digital subscriber line transmission system operated through a hybrid circuit is a configurational example of a digital subscriber line transmission system.
FIG. 1 shows a configurational example of the above described digital subscriber line transmission system.
An encoder (COD) 101 converts binary digital transmission data to a transmission code (for example, a 2B1Q code).
A line driver unit (DRV) 102 drives a subscriber line 104 to transmit a transmission code.
A hybrid unit ( HYB ) 103 performs a two-wire/four-wire conversion between the two-wire subscriber line 104 and a two-wire transmission line 105 or a two-wire receiving line 106.
An A/D converting unit (ADC) 107 converts a signal, a combination of the echo of a transmission signal leaked through the hybrid unit 103 and the received signal (an analog signal) sent from the correspondent and attenuated in the subscriber line 104, to a digital signal.
An echo canceler (EC) 108 and an adder 109 cancel the above described echo.
A jitter compensating circuit (JC) 110 and an adder 111 compensate the echo leaked through the echo canceler 108 when the phase of a sampling timing signal 114 of the A/D converting unit 107 generated by a timing regenerating circuit 113 described later jumps.
An equalizer (EQL) 112 equalizes a received signal sent from the correspondent and attenuated in the subscriber line 104.
The timing regenerating circuit (TIM) 113 regenerates from the received signal the sampling timing signal 114 of the A/D converting unit 107.
In the two-wire digital subscriber line transmission system having a hybrid circuit configured as described above, an echo leaks from a sending side to a receiving side through the hybrid unit 103. The received signal transmitted through the subscriber line 104 is attenuated considerably. Therefore, the intensity ratio of an echo to a received signal may reach several tens of decibels. Accordingly, in the above described transmission, echoes must be canceled in the echo canceling process by the echo canceler 108 and the jitter compensating circuit 110.
FIG. 2 shows an example of the configuration of the echo canceler 108 and the adder 109 shown in FIG. 1.
In FIG. 2, X.sub.j is an inputted echo at discrete time j (hereinafter referred to as time 3), ER.sub.j is an echo replica generated at time j, a.sub.j is a transmission symbol at time j, C.sub.0 -C.sub.N are tap coefficients, and .epsilon..sub.j is a signal of an error between an inputted echo X.sub.j and the echo replica ER.sub.j.
First, the echo replica ER.sub.j is calculated using the following expression by the configuration containing a delay circuit 202 for delaying a signal by 1 sampling timing T, a multiplier 203, and an adder 204. "*" indicates a multiplication. ##EQU1##
The error signal .epsilon..sub.j is calculated by the adder (subtracter) 109 using the following expression. EQU .epsilon..sub.j =X.sub.j -ER.sub.j ( 2)
A tap coefficient update unit 201 updates tap coefficients C.sub.0 -C.sub.N to attenuate the above described error signal .epsilon..sub.j. The following expression shows an example of a tap coefficient updating algorithm, where .alpha. indicates a constant. ##EQU2##
Next, timing regeneration control in the transmission system comprising the digital subscriber line transmission system shown in FIG. 1 is explained.
First, digital subscriber line transmission systems shown in FIG. 1 are provided on the sides of a station and a subscriber face to face with each other connected by the subscriber line 104.
In the transmission system on the station side, transmission data are transmitted after being encoded by the encoder 101 in synchronism with a local oscillation clock generated by its own oscillator, while received data are A/D converted by the A/D converting unit 107 according to the sampling timing signal 114 regenerated from a received signal by the timing regenerating circuit 113. In the transmission system on the subscriber side, received data are, as on the station side, A/D converted by the A/D converting unit 107 according to the sampling timing signal 114 regenerated from a received signal by the timing regenerating circuit 113. Transmission data are, unlike on the station side, sent after being encoded by the encoder 101 in synchronism with the above described sampling timing signal 114.
When the timing regenerating circuit 113 changes the phase of the regenerated reception timing, the regenerated reception timing gives a change in the phase of the transmission timing before and after its own change in the transmission system on the station side. However, in the transmission system on the subscriber side, the regenerated reception timing gives a change in the phase of the transmission timing before its own change, but does not give a change in the phase of the transmission timing after its own change.
If the timing regenerating circuit 113 controls the phase of the sampling timing signal 114 provided for the A/D converting unit 107 in the DPLL (digitally phase locked loop) method, the phase of the sampling timing signal 114 jumps during the control process, wherein a jitter may be caused.
The jitter is compensated for by the jitter compensating circuit 110 and the adder 111 shown in FIG. 1. FIG. 3 shows an example of the configuration containing the jitter compensating circuit 110 and the adder 111.
In FIG. 3, The EC 108 and the adder 109 are the same as those shown in FIG. 1. F.sub.j is a residue as uncancelled echo at time j; JR.sub.j is a jitter compensating replica generated at time j; a.sub.j is a transmission symbol at time j; J.sub.0 -J.sub.K are tap coefficients; and .epsilon..sub.j ' is a signal of an error between the residue as uncanceled echo F.sub.j and the jitter compensating replica JR.sub.j at time j. D indicates jitter directional data instructed by the timing regenerating circuit 113, and shows -1 when controlling a fast phase, +1 when controlling a delayed phase, and - when no control is performed.
In this case, the phase of the sampling timing signal 114 regenerated on the receiving side of the transmission system of the station is relatively changed by the timing signal generated uniquely by the local oscillator on the transmission side. Therefore, an echo is canceled and a jitter is compensated in the transmission on the station side based on the following principle.
Assume, for simplification of explanation, that the echo canceler 108 and the adder 109 (refer to FIGS. 1 and 2) cancel at each sampling timing each of the echo components, which are generated based on a transmission symbol outputted by the encoder 101 at a transmission timing and sampled by the A/D converting unit 107 at each of the timing t.sub.0, t.sub.1, t.sub.2, . . . , for example, shown in FIG. 4, using the echo replica components generated based on the tap coefficients C.sub.0, C.sub.1, C.sub.2.
At sampling timing t.sub.0, for example, the timing regenerating circuit 113 is assumed to cause the phase of the sampling timing signal 114 to jump forward or backward to the relative phase P or M, before or after the relative phase 0.
If the relative phase of the sampling timing signal 114 is 0, an echo component can be canceled as shown in FIG. 4 only by an echo replica component according to a tap coefficient C.sub.0 from the echo canceler 108 at timing T.sub.0. Hereafter, at each of the timing t.sub.1, t.sub.2 . . . , an echo component can be canceled only by an echo replica component according to a tap coefficient C.sub.0 from the echo canceler 108.
Actually, echo is generated continuously according to each transmission symbol outputted by the encoder 101 at each transmission timing. On the receiving side, echoes generated at each transmission timing are composed and A/D converted. Thus, at one sampling timing, an echo component composed at the timing is canceled by a sum ER.sub.j (FIG. 2) of the echo replica components according to a plurality of tap coefficients C.sub.0 -C.sub.N from the echo canceler 108.
If the relative phase of the sampling timing signal 114 jumps to P, an echo component can be canceled at timing t.sub.0 by the echo replica component according to the tap coefficient C.sub.0 from the echo canceler 108 and the jitter compensating replica component according to the tap coefficient J.sub.OP from the jitter compensating circuit 110. Hereinafter, at each of the timing t.sub.1, t.sub.2 . . . , an echo component at each timing can be canceled by each of the echo replica components according to each of the tap coefficients C.sub.1, C.sub.2 . . . from the echo canceler 108, and by each of the jitter compensating replica components according to each of the tap coefficients J.sub.1p, J.sub.2p, . . . from the jitter compensating circuit 110.
In this case, composed echo components each being generated continuously according to each of the transmission symbols are A/D converted on the receiving side. Therefore, at one sampling timing, the composed echo components at the timing can be canceled by the sum ER.sub.j of echo replica components according to a plurality of tap coefficients C.sub.0 -C.sub.N from the echo canceler 108, and the sum JR.sub.j (FIG. 3) of the jitter compensating replica components according to a plurality of tap coefficients J.sub.0 -J.sub.K from the jitter compensating circuit 110.
Likewise, when the relative phase of the sampling timing signal 114 Jumps to M, an echo can be canceled at timing t.sub.0 by the echo replica component according to the tap coefficient C.sub.0 from the echo canceler 108, and the jitter compensating component according to the tap coefficient J.sub.0M from the jitter compensating circuit 110. Hereinafter, at each timing t.sub.1, t.sub.2, an echo component can be canceled at each timing by each of the jitter compensating replica components according to each of the tap coefficients C.sub.1, C.sub.2, . . . from the echo canceler 108, and each of the jitter compensating replica components according to each of the tap coefficients J.sub.1M -J.sub.2M, . . . from the jitter compensating circuit 110.
In this case, each of the echo components are continuously generated according to each of the transmission symbols, composed, and then A/D converted on the receiving side. Therefore, at a sampling timing, composed echo components are canceled by the sum ER.sub.j of echo replica components according to a plurality of tap coefficients C.sub.0 -C.sub.N from the echo canceler 108, and the sum JR.sub.j of jitter compensating replica components according to a plurality of tap coefficients J.sub.0 -J.sub.K from the jitter compensating circuit 110.
According to the principle of the above described jitter compensation, the jitter compensation replica JR.sub.j can be calculated as follows by a delay circuit 302 for delaying a signal by 1 sampling timing T, multipliers 303 and 304, and an adder 305, shown in FIG. 3, in the jitter compensating circuit 110 of the transmission system on the station side. ##EQU3##
In a small phase range where the relative phase of the sampling timing signal 114 jumps through the timing regenerating circuit 113, an approximation of an echo component can be obtained by a linear increment/decrement. Therefore, each of the tap coefficients J.sub.0P, J.sub.1P, J.sub.2P, . . . when the relative phase of the sampling timing signal 114 Jumps to P and each of the coefficients J.sub.0M, J.sub.1M -J.sub.2M, . . . when the relative phase of the sampling timing signal 114 jumps to M can be approximated to be equal in value, but with an opposite sign respectively.
According to the fact, the jitter compensating circuit 110 shown in FIG. 3, a tap coefficient can be obtained to generate a jitter compensating replica JR.sub.j by multiplying each of the tap coefficients J.sub.0, J.sub.1, J.sub.2, . . . by a value in data D (-1, 0, or +1)for indicating the direction of a jitter as instructed by the timing regenerating circuit 113 by each of the multipliers 304 as shown by the above described expression 4.
Next, an error signal .epsilon..sub.j is obtained by the adder (subtracter) 111 using the following expression. EQU .epsilon..sub.j =X.sub.j -ER.sub.j -JR.sub.j ( 5)
A tap coefficient update unit 301 updates tap coefficients J.sub.0 -J.sub.K to reduce the above described error signal .epsilon..sub.j '. The following expression shows an example of an algorithm for updating a tap coefficient, where .beta. indicates a constant. ##EQU4##
In the explanation above, the timing regenerating circuit 113 causes jitters at the relative phase P or M (before or after the relative phase 0) in the transmission system on the station side. However, when a phase is shifted continuously, for example, during the training for a timing regeneration, the phase is shifted after each of the tap coefficients in the jitter compensating circuit 110 is converged, and simultaneously each of the tap coefficients used by the echo canceler 108 is modified by the following expression. Repeating this process prevents a residual error from growing, thereby successfully shifting the sampling phase. EQU C.sub.k =C.sub.k +J.sub.k .multidot.D (7)
Next, the operation of canceling an echo and compensating a jitter in the transmission system on the subscriber side is explained.
On the subscriber side, transmission data are transmitted by the encoder 101 in synchronism with the sampling timing signal 114 on the receiving side using a received signal regenerated by the timing regenerating circuit 113. Therefore, an echo generated based on a transmission symbol transmitted before the generation of a jitter is canceled by an echo replica from the echo canceler 108 and a jitter compensating replica from the jitter compensating circuit 110. By contrast, an echo generated based on a transmission symbol transmitted after the generation of a jitter can be canceled only by an echo replica from the echo canceler 108 because, in this case, a phase difference does not exist between the sending side and the receiving side.
In the A/D converting unit 107, an echo component sampled at timing t.sub.0 shown in FIG. 5, for example, is composed of each echo component, as shown in FIG. 5, generated based on each of the transmission symbols at t.sub.0 and the preceding timing . . . , t.sub.-2, and t.sub.-1. Likewise, the echo component sampled at timing t.sub.1 is composed of each echo component generated based on each of the transmission symbols at timing t.sub.1 and the preceding timing . . . , t.sub.-2, t.sub.-1, and t.sub.0. Generally, the echo component sampled at timing t.sub.j following timing t.sub.0 is composed of each echo component generated based on each of the transmission symbols at timing t.sub.j and the preceding timing . . . , t.sub.-2, t.sub.-1, t.sub.0, . . .
Accordingly, when the timing regenerating circuit 113 causes the phase of the sampling timing signal 114 to jump to the relative phase P or M (before or after the relative phase 0) at timing t.sub.0 in FIG. 5 as in FIG. 4, for example, each echo component generated based on each transmission symbol transmitted at the timing preceding timing t.sub.0, that is, timing . . . , t.sub.-2, and t.sub.-1 can be canceled at any of the following timings t.sub.j (where 0.ltoreq.j.ltoreq.K-1) by each of the echo replica components based on each of the tap coefficients C.sub.N, C.sub.N-1, . . . , C.sub.1+j from the echo canceler 108 and by each of the jitter compensating replica components based on each of the tap coefficients J.sub.K, . . . , J.sub.1+j from the jitter compensating circuit 110. Each echo component generated based on each transmission symbol transmitted at each of the timings t.sub.0 and the following timings t.sub.1, . . . , t.sub.j can be canceled by each of the echo replica components based on each of the tap coefficients C.sub.j, . . . , C.sub.0 from the echo canceler 108.
The echo component generated before timing t.sub.-N is attenuated sufficiently to be ignored. The jitter compensation component before timing t.sub.-K (N&gt;K, that is, t.sub.-N &lt;t.sub.-K) is also small enough to be ignored.
When the timing regenerating circuit 113 causes the phase of the sampling timing signal 114 to jump at timing 0 (=t.sub.0) according to the principle of the above described jitter compensation, the jitter compensating replica JR.sub.j generated at the following timing j (=t.sub.j, 0.ltoreq.j.ltoreq.K) by the jitter compensating circuit 110, shown in FIG. 3, in the transmission system on the subscriber side can be obtained by the following expression. ##EQU5##
That is, the adder 305, shown in FIG. 3, in the jitter compensating circuit 110 selects and adds the outputs from the (l+j)th through K-th multipliers 304 out of the outputs from the 0-th through the K-th multipliers 304 in order to generate a jitter compensating replica JR.sub.j represented by expression 8 above.
An error signal .epsilon..sub.j ' is obtained by the adder (subtracter) 111 using the following expression as obtained by expression 5 described above. EQU .epsilon..sub.j =X.sub.j -ER.sub.j -JR.sub.j ( 9)
The tap coefficient update unit 301 updates the tap coefficients J.sub.l+j through J.sub.K to reduce the value of the above described error signal .beta..sub.j '. The following expression shows an example of the tap coefficient updating algorithm. .epsilon. is a constant. ##EQU6##
Since the jitter compensation component at time j (K&lt;j) can be assumed to be small enough to be ignored as described above, an output of the jitter compensating replica JR.sub.j from the jitter compensating circuit 110 is controlled to stop by a control circuit (not shown in the drawings) at time J (K&lt;j).
An impulse response of an echo leaked from the sending side to the receiving side takes a long time in the digital subscriber line transmission system configured as shown in FIG. 1. Therefore, the length of a tap coefficient N in the echo canceler 108 and the length of a tap coefficient K in the jitter compensating circuit 110 indicate a large value if no special actions are taken.
Then, the impulse response of an echo must be made short by inserting a high-pass filter between the A/D converting unit 107 and the adder 109 shown in FIG. 1 so that the length of each tap coefficient in the echo canceler 108 and the jitter compensating circuit 110 can be shortened.
However, if the above described filter is mounted, the A/D conversion results before and after the generation of the jitter are included in the output of the filter immediately after the generation of a jitter. As a result, in the conventional jitter compensating circuit having the configuration shown in FIG. 3, it cannot be determined from what time point of the residual echo the component of the jitter compensating replica from the circuit should be removed, thereby causing a problem that the jitter cannot be compensated at all.